1. Field of Invention
The present invention relates to a CMOS image sensor, and, more particularly, to a CMOS image sensor that outputs data in a block scanning fashion, which can process without needing a preprocessing operation.
2. Description of Related Art
In an image system using an image sensor such as a CCD, raster scanning as shown in FIG. 1 is used because of the limitation associated with the device. When a still image is compressed according to the JPEG standard, which is a widely used standard, or when a moving image is compressed according to the MPEG standard, which is also widely used, Discrete Cosine Transform (DCT) is performed for a unit (block) including 8 pixels in a row by 8 pixels in a column. To this end, data associated with all pixels is first stored into a high-capacity frame memory, and then block-scanning is performed as shown in FIG. 2.
CMOS image sensors are now receiving attention because of their advantages over CCD image sensors. In a paper entitled “CMOS Active Pixel Image Sensors for Highly Integrated Imaging System,” Sunetra K. Mendis et al., Journal of Solid-State Circuits, Vol. 32, No. 2, February 1997, pp. 187–197, a pixel sensor is disclosed which includes a photogate PG having a floating diffusion (FD) output FD isolated by a transfer gate TX, as shown in the circuit diagram of FIG. 3 and also in the timing chart of FIG. 4. In addition to the photogate PG, this pixel sensor also includes a reset transistor MR, an in-pixel source follower MIN, and a row selection transistor MX.
A reading circuit is used in common for all pixels in the same row. Each reading circuit includes a load transistor MLN of a first source follower, and two sample-and-hold circuits for storing a signal voltage and a reset voltage, respectively. To reduce random noise or fixed pattern noise in the pixel sensor and the reading circuit, it is effective to perform correlated double sampling in which a reset voltage containing noise and a signal voltage containing the same noise are sampled in a short period of time during which the noise in the reset voltage and the noise in the signal voltage have strong correlation with each other, and the reset voltage is subtracted from the signal voltage. By this correlated double sampling, it is possible to suppress reset noise and 1/f noise contained in the signal output from floating diffusion node of the pixel and also suppress a variation in threshold of the in-pixel source follower.
Each sample-and-hold circuit includes sample-and-hold switches MSHS and MSHR, and capacitors CS and CR. To buffer capacitor voltages and read them out via a horizontal bus having high capacitance, each sample-and-hold circuit further includes row source followers MP1 and MP2 and row selection transistors MY1 and MY2. Load transistors MLP1 and MLP2 of the row source followers are used in common for all pixels in a pixel array. In a row reading circuit, a p-channel source follower is used to compensate for a change in the signal voltage caused by an n-channel source follower in a pixel.
The operation of the CMOS image sensor is performed as shown in FIG. 5. That is, first, power supply voltages VDD and VSS are set to 5 V and 0 V, respectively, and the transfer gate TX is biased to 2.5V. The load transistor MLN of the in-pixel source follower and the load transistors MLP1 and MLP2 of the row source followers are biased to DC voltages of 1.5 and 2.5 V, respectively.
During a signal accumulation period shown in FIG. 5A, electrons generated by light are accumulated in the surface channel photogate PG biased at 5 V. Herein, the reset transistor MR is biased at 2.5 V so that it serves as a lateral antiblooming drain into which an excess signal charge is drained. On the other hand, the column selection transistor MX is biased at 0 V. After accumulating the signal charges, the signal charges of pixels are read on a column-to-column basis.
More specifically, first, pixels in a particular column are addressed by turning on a corresponding column selection switch MX. Then, as shown in FIG. 5B, the reset gate MR of a pixel is temporarily set to 5 V thereby resetting the floating diffusion output node FD of that pixel. As a result, the floating diffusion output FD is reset to about 3.5 V.
The sample-and-hold switch MSHR is turned on thereby sampling the output of the first source follower and holding it in the capacitor CR. Then, as shown in FIG. 5C, the bottom of the potential well of the photogate PG is temporarily raised so as to transfer the charge accumulated by the photocurrent to FD. Then, as shown in FIG. 5D, the sample-and-hold switch MSHS is turned on thereby holding the signal voltage of FD in the capacitor CS of the reading circuit.
The row selection switches MY1 and MY2 are then turned on sequentially so that the reset voltage and the signal voltage held are read sequentially via the second source follower.
Finally, The FD reset signal R and the transfer signal TX are temporally turned on, thereby resetting the photodiode and again inputting light.
In the paper titled “Image Compression CMOS Image Sensor Based on an Analog Two-Dimensional DCT Circuit and an Accuracy Adaptive A/D Converter,” presented by Shoji Kawato et al. in Proceedings of the Institute of Image Information and Television Engineers, Vol. 52, No. 2, pp. 206–213 (1998), a CMOS image sensor is disclosed in which an analog two-dimensional DCT circuit is integrated with the CMOS image sensor so that image compression is performed on the image sensor. In this CMOS image sensor, as shown in FIG. 6, two pass transistors Tv and Th are connected in series to a photodiode PD of a pixel sensor 10. One pass transistor (Tv) is activated by a row block selection signal Vscan output from a row (vertical) block scanner Vs, and the other pass transistor (Th) is activated on a column-to-column basis by a column selection signal Hscan output from a column (horizontal) scanner Vh, thereby addressing eight pixels so as to read a signal on a block-to-block basis and directly perform two-dimensional DCT operation in an analog area.
In a peripheral circuit, there are disposed a plurality of pass transistors (coupling transistors) Tc, which are selected on a block-to-block basis. Signal charges of a photodiode PD serving as photosensors are sequentially transferred via a total of three pass transistors Tv, Th, and Tc to feedback capacitors Cf1 and Cf2 of a two-stage amplifier including stages A1 and A2 in a reading circuit SCC based on a switched capacitor technique.
The output of the reading circuit SCC is subjected to an analog operation in the two-dimensional DCT circuit (not shown) and then converted from analog form into digital form.
In FIG. 6, ISA denotes an image sensor array.
A problem of the former known technique described above is that reading cannot be performed on a block-to-block basis.
On the other hand, in the latter known technique described above, the photodiode cannot be reset, and thus there is large random noise. Furthermore, because the signal voltage is not amplified in the pixel sensor 10 shown in FIG. 6, the signal is inevitably contaminated with 1/f noise when being passed through three pass transistors, and also contaminated with coupling noise when being transmitted via a long interconnection line to the peripheral circuit. Another problem is that color correction and motion detection are impossible, because only analog data subjected to two-dimensional DCT operation is available.